MC10H107: Triple 2-Input XOR/XNOR Gate _ BDTIC a Leading Distributor in China

MC10H107: Triple 2-Input XOR/XNOR Gate

The MC10H107 is a triple 2-input exclusive OR/NOR gate. This MECL 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power-supply current.

Features

Propagation Delay, 1.0 ns Typical
Power Dissipation 35 mW/Gate Typical (same as MECL 10K)
Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
Voltage Compensated
MECL 10K Compatible
Pb-Free Packages are Available

Application Notes (16)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Family Characteristics for MECL 10H™ and MECL 10K™	TND309/D (248.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
Triple 2-Input Exclusive OR/Exclusive NOR Gate	MC10H107/D (130kB)	8	Aug, 2016

Simulation Models (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC10H107L	MC10H107L.IBS (5.0kB)	0
IBIS Model for MC10H107P	MC10H107P.IBS (5.0kB)	0

Package Drawings (2)

Document Title	Document ID/Size	Revision
20 LEAD PLLC	775-02 (60.9kB)	F
PDIP-16	648-08 (34.2kB)	V

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
MC10H107FNR2G	Last Shipments	Pb-free Halide free	PLLC-20	775-02	3	Tape and Reel	500
MC10H107PG	Active	Pb-free Halide free	PDIP-16	648-08	NA	Tube	25	Contact BDTIC

Specifications

Product	Type	Channels	Input Level	Output Level	VCC Typ (V)	fToggle Max (MHz)	tpd Typ (ns)	tJitter Typ (ps)	tR & tF Max (ps)
MC10H107PG	XOR/XNOR	3	ECL	ECL	-5.2		1		1500

Triple 2-Input Exclusive OR/Exclusive NOR Gate (130kB) MC10H107

AC Characteristics of ECL Devices NB100LVEP91

Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91

Clock Management Design Using Low Skew and Low Jitter Devices MC10H604

Designing with PECL (ECL at +5.0 V) NB100LVEP91

ECL Clock Distribution Techniques NB100LVEP91

ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91

Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604

Interfacing Between LVDS and ECL NB100ELT23L

Interfacing with ECLinPS NB100LVEP91

Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201

Phase Lock Loop General Operations MC10H604

Storage and Handling of Drypack Surface Mount Device NB3U23C

Termination of ECL Logic Devices NB100LVEP91

The ECL Translator Guide NB100LVEP91

Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91

Using Wire-OR Ties in ECLInPS™ Designs MC10H351

IBIS Model for MC10H107L MC10H107

IBIS Model for MC10H107P MC10H107

20 LEAD PLLC MC10H351

PDIP-16 MC10H350

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