MC10H125: Quad ECL to TTL Translator

The MC10H125 is a quad translator for interfacing data and control signals between the MECL section and saturated logic section of digital systems. The 10H part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power-supply current. Outputs of unused translators will go to low state when their inputs are left open.

Features
  • Propagation Delay, 2.5 ns Typical
  • Voltage Compensated
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • MECL 10K Compatible
  • Pb-Free Packages are Available
Application Notes (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
Simulation Models (2)
Document TitleDocument ID/SizeRevisionRevision Date
H124, 125, 350-352 Translator I/O SPICE Modelling KitAN1598/D (105.0kB)1
IBIS Model for MC10H125PMC10H125P.IBS (7.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Quad MECL-to-TTL TranslatorMC10H125/D (144kB)14Aug, 2016
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC10H125FNGActivePb-free Halide freePLLC-20775-023Tube46Contact BDTIC
MC10H125FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500Contact BDTIC
MC10H125PGActivePb-free Halide freePDIP-16648-08NATube25Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10H125FNG4ECLTTL5502.11200
MC10H125FNR2G4ECLTTL5502.11200
MC10H125PG4ECLTTL5502.11200
Quad MECL-to-TTL Translator (144kB) MC10H125
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
H124, 125, 350-352 Translator I/O SPICE Modelling Kit MC10H351
IBIS Model for MC10H125P MC10H125
20 LEAD PLLC MC10H351
PDIP-16 MC10H350
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