NB100LVEP17: Quad Differential Driver/Receiver/Buffer

The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.Inputs of unused gates can be left open and will not affect the operation of the rest of the device.

Features
  • 250 ps Typical Propagation Delay
  • Maximum Frequency >2.5 GHz Typical
  • Flow through Pinout
  • PECL Mode Operating Range: VCC = 2.375 V to 3.8 V, with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V, with VEE = -2.375 V to -3.8 V
  • Q Output will Default LOW with Inputs Open or at VEE
  • VBB Output
Application Notes (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Package Drawings (2)
Document TitleDocument ID/SizeRevision
QFN24, 4x4, 0.5P485L-01 (60.0kB)B
TSSOP-20 WB948E-02 (39.7kB)D
Evaluation Board Documents (1)
Document TitleDocument ID/SizeRevisionRevision Date
Evaluation Board User's Manual for High Frequency TSSOP 20EVBUM2057/D (247.0kB)2
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V / 3.3V ECL Quad Differential Driver/ReceiverNB100LVEP17/D (99kB)8
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
ECLTSSOP20EVBActiveHigh Frequency TSSOP20 Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB100LVEP17DTObsoletePb-freeTSSOP-20948E-021Tube75
NB100LVEP17DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
NB100LVEP17DTR2ObsoletePb-freeTSSOP-20948E-021Tape and Reel2500
NB100LVEP17DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
NB100LVEP17MNGActivePb-free Halide freeQFN-24485L-011Tube92Contact BDTIC
NB100LVEP17MNR2GActivePb-free Halide freeQFN-24485L-011Tape and Reel3000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB100LVEP17DTGSignal Driver41:1ECL CML LVDSECL3.3 2.5 50.5250.2522525002500
NB100LVEP17DTR2GSignal Driver41:1ECL CML LVDSECL3.3 5 2.50.5250.2522525002500
NB100LVEP17MNGSignal Driver41:1CML ECL LVDSECL5 3.3 2.50.5250.2522525002500
NB100LVEP17MNR2GSignal Driver41:1CML LVDS ECLECL5 2.5 3.30.5250.2522525002500
2.5V / 3.3V ECL Quad Differential Driver/Receiver (99kB) NB100LVEP17
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for NB100LVEP17MN -3.3V NB100LVEP17
IBIS Model for nb100lvep17dt 2.5V NB100LVEP17
IBIS Model for nb100lvep17dt 3.3V NB100LVEP17
IBIS Model for nb100lvep17mn 3.3V NB100LVEP17
EVBUM2057/D - 247 ECLTSSOP20EVB
TSSOP-20 WB NLSX3018
QFN24, 4x4, 0.5P NCN8026