NB3L853141: 1-TO-5 DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER

The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer designed explicitly for low output skew applications. The NB3L853141 features a multiplexed input which can be driven by either a differential or single-ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The SEL pin will select the differential clock inputs, CLK0 & CLK0, when LOW (or left open and pulled LOW by the internal pull-down resistor). When SEL is HIGH, the single-ended CLK1 input is selected. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Features
  • CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL,LVHSTL, SSTL, LVCMOS
  • CLK1 can Accept LVCMOS and LVTTL
  • 700 MHz Maximum Clock Output Frequency
  • Five Differential LVPECL Clock Outputs
  • 30 ps Max. Skew Between Outputs
  • 1.5 ns Maximum Propagation Delay
  • Operating Range: VCC = 2.375 V to 3.8 V
  • Synchronous Clock Enable
  • 40C to +85C Ambient Operating Temperature Range
Applications
  • Computing
  • Telecom
  • Backplanes
End Products
  • Routers
  • Servers
  • Switches
Application Notes (5)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Semiconductor Package Thermal CharacterizationAND8215/D (363.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V/3.3V 1:5 LVPECL Fanout BufferNB3L853141/D (107kB)2
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3L853141 IBIS ModelNB3L853141.ibs (140kB)1Sep, 2015
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP-20 WB948E-02 (39.7kB)D
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3L853141DTGActivePb-free Halide freeTSSOP-20948E-021Tube75Contact BDTIC
NB3L853141DTR2GActivePb-free Halide freeTSSOP-20948E-021Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3L853141DTGBuffer12:1:5HCSL LVCMOS LVPECL LVDS LVTTL SSTL LVHSTLLVPECL2.5 3.30.05301700700
NB3L853141DTR2GBuffer12:1:5HCSL LVDS SSTL LVHSTL LVCMOS LVPECL LVTTLLVPECL2.5 3.30.05301700700
2.5V/3.3V 1:5 LVPECL Fanout Buffer (107kB) NB3L853141
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Semiconductor Package Thermal Characterization NGTB15N60EG
Storage and Handling of Drypack Surface Mount Device NB3U23C
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
NB3L853141 IBIS Model NB3L853141
TSSOP-20 WB NLSX3018