The NB3N106K is a differential 1:6 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N106K is designed with HCSL clock distribution and FBDIMM applications in mind.
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Document Title | Document ID/Size | Revision | Revision Date |
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A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges | AND9202/D (179kB) | 1 | Mar, 2015 |
Board Level Application Notes for DFN and QFN Packages | AND8211/D (175.0kB) | 1 | |
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) | AND8086/D (40.0kB) | 0 | |
Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
Semiconductor Package Thermal Characterization | AND8215/D (363.0kB) | 0 | |
Storage and Handling of Drypack Surface Mount Device | AND8003/D (49kB) | 2 | Mar, 2016 |
Document Title | Document ID/Size | Revision |
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QFN24, 4x4, 0.5P | 485L-01 (60.0kB) | B |
Document Title | Document ID/Size | Revision | Revision Date |
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Fanout Clock and Data Driver, 3.3 V Differential in 1:6, with HCSL Outputs | NB3N106K.PDF (152.0kB) | 5 |
Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit | ||
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NB3N106KMNG | Active | Pb-free Halide free | QFN-24 | 485L-01 | 1 | Tube | 92 | Contact BDTIC |
NB3N106KMNR2G | Active | Pb-free Halide free | QFN-24 | 485L-01 | 1 | Tape and Reel | 3000 | Contact BDTIC |
Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
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NB3N106KMNG | Buffer | 1 | 1:6 | ECL LVDS CMOS HCSL TTL | HCSL | 3.3 | 0.1 | 100 | 0.8 | 400 | 400 | 400 |
NB3N106KMNR2G | Buffer | 1 | 1:6 | ECL LVDS TTL CMOS HCSL | HCSL | 3.3 | 0.1 | 100 | 0.8 | 400 | 400 | 400 |