NB3N1900K: 3.3 V 100/133 MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe

The NB3N1900K differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1900K supports HCSL output levels.

Features
  • Fixed Feedback Path for Lowest Input−to−Output Delay
  • Eight Dedicated OE# Pins for Hardware Control of Outputs
  • PLL Bypass Configurable for PLL or Fanout Operation
  • Selectable PLL Bandwidth
  • Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI
  • SMBus Programmable Configurations
  • 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
  • 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
  • Cycle−to−Cycle Jitter: < 50 ps
  • Output−to−Output Skew: < 65 ps
  • Input−to−Output Delay: Fixed at 0 ps
  • Input−to−Output Delay Variation: < 50 ps
  • Phase Jitter: PCIe Gen3 < 1 ps rms
  • Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
  • QFN 72−pin Package, 10 mm x 10 mm
  • These are Pb−Free Devices
Applications
  • Industrial
  • Networking
  • Computing
  • Consumer
End Products
  • Desktop
  • Notebook
  • Switchers/Routers
  • Servers
  • Set Top Box
  • Automated Test Equipment
Application Notes (1)
Document TitleDocument ID/SizeRevisionRevision Date
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing ChallengesAND9202/D (179kB)1Mar, 2015
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN72 10x10, 0.5P485DK (58.2kB)O
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N1900K IBIS Modelnb3n1900k.ibs (72kB)3.1Sep, 2014
Evaluation Board Documents (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N1900K Evaluation Board User's ManualEVBUM2256/D (270kB)1Oct, 2014
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V 100/133 MHz Zero Delay Buffer/Fanout Buffer for PCIe 1 Input 19 HCSL Differential OutputsNB3N1900K/D (205kB)4Jul, 2016
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3N1900KMNGActivePb-free Halide freeQFN-72485DK3Tray JEDEC168Contact BDTIC
NB3N1900KMNTWGActivePb-free Halide freeQFN-72485DK3Tape and Reel1000Contact BDTIC
NB3N1900KMNTXGActivePb-free Halide freeQFN-72485DK3Tape and Reel1000Contact BDTIC
Specifications
ProductInput LevelOutput LevelOutputs Per ChannelVDD Typ (V)tskew(O-O) Max (ps)F Max (MHz)tJitter Max (ps)
NB3N1900KMNGHCSLHCSL193.385133.3350
NB3N1900KMNTWGHCSLHCSL193.385133.3350
NB3N1900KMNTXGHCSLHCSL193.385133.3350
3.3V 100/133 MHz Zero Delay Buffer/Fanout Buffer for PCIe 1 Input 19 HCSL Differential Outputs (205kB) NB3N1900K
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges NCN2612B
NB3N1900K IBIS Model NB3N1900K
NB3N1900K Evaluation Board User's Manual NB3N1900K
QFN72 10x10, 0.5P NB3N1900K
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