NB3W1900L: 3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible Push‐Pull Clock ZDB/Fanout Buffer for PCIe

The NB3W1900L differential clock buffers are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point-to-point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3.The NB3W1900L internal PLL is optimized to support 100MHz and 133 MHz frequency operation. The NB3W1900L is developed with the low-power NMOS Push-Pull buffer type.

Features
  • 19 Low Power Differential Clock Output Pairs @ 0.7 V
  • Output-to-Output Skew Performance: < 85 ps
  • Cycle-to-Cycle Jitter (PLL Mode): < 50ps
  • Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
  • Input-to-Output Delay Variation: < 50 ps
  • Fixed-Feedback for Lowest Input-to-Output Delay Variation
  • Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
  • 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2/ Gen3 and Intel QPI Phase Jitter
  • Individual OE Control via SMBus
  • Low-Power NMOS Push-Pull HCSL−Compatible Outputs
  • PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
  • SMBus Address Configurable to Allow Multiple Buffers in a Single Control Network
  • Programmable PLL Bandwidth
  • Two Tri-level Addresses Selection (Nine SMBus Addresses)
  • QFN 72-pin Package, 10 mm × 10 mm
  • These are Pb-Free Devices
Applications
  • Industrial
  • Networking
  • Computing
  • Consumer
End Products
  • Desktop
  • Notebook
  • Switches / Routers
  • Servers
  • Set Top Box
  • Automated Test Equipment
Application Notes (1)
Document TitleDocument ID/SizeRevisionRevision Date
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing ChallengesAND9202/D (179kB)1Mar, 2015
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V 100 MHz/133 MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer forPCIeNB3W1900L/D (175kB)1
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3W1900L IBIS Modelnb3w1900l.ibs (64kB)3.2Sep, 2014
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN72 10x10, 0.5P485DK (58.2kB)O
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3W1900LMNGActivePb-free Halide freeQFN-72485DK3Tray JEDEC168Contact BDTIC
NB3W1900LMNTXGActivePb-free Halide freeQFN-72485DK3Tape and Reel1000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3W1900LMNGBuffer11:19HCSLHCSL3.30.002 0.001 0.0485087.5133.33 100
NB3W1900LMNTXGBuffer11:19HCSLHCSL3.30.001 0.04 0.00285087.5100 133.33
3.3 V 100 MHz/133 MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer forPCIe (175kB) NB3W1900L
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges NCN2612B
NB3W1900L IBIS Model NB3W1900L
QFN72 10x10, 0.5P NB3N1900K
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