NB3W800L: 3.3 V 100/133 MHz Differential 1:8 HCSL Compatible Push-Pull Clock ZDB/Fanout Buffer for PCIe

The NB3W800L is a low−power 8−output differential buffer that meets all the performance requirements of the DB800ZL specification. The NB3W800L is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. A fixed, internal feedback path maintains low drift for critical QPI applications.

Features

8 Differential Clock Output Pairs @ 0.7 V
Low−power NMOS Push−pull HCSL Compatible Outputs
Output−to−output Skew <50 ps
Input−to−output Delay Variation <100 ps
PCIe Gen3 Phase Jitter <1.0 ps RMS
QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS
Individual OE Control; Hardware Control of Each Output
PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
100 MHz or 133 MHz PLL Mode Operation; Supports PCIe and QPI Applications
Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream PLL’s
Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
SMBus Programmable Configurations

Applications

Industrial
Networking
Computing
Consumer

End Products

Desktop
Notebook
Switches / Routers
Servers
Automated Test Equipment

Simulation Models (1)

Document Title	Document ID/Size	Revision	Revision Date
NB3W800L	NB3W800L (66kB)	0	May, 2015

Package Drawings (1)

Document Title	Document ID/Size	Revision
QFN48 6.0x6.0, 0.4P	485DP (33.4kB)	O

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
Differential 1:8 Push-Pull Clock ZDB/Fanout Buffer for PCIe, 3.3 V, 100/133 MHz	NB3W800L/D (146kB)	2	Jul, 2016

Evaluation Board Documents (5)

Document Title	Document ID/Size	Revision Date
NB3W800LMNGEVB Bill Of Materials (ROHS Compliant)	NB3W800LMNGEVB_BOM_ROHS.pdf (40kB)
NB3W800LMNGEVB GUI Evaluation Board User's Manual	EVBUM2330/D (438kB)	Nov, 2015
NB3W800LMNGEVB Schematic	NB3W800LMNGEVB_SCHEMATIC.pdf (356kB)
NB3W800LMNGEVB Test Procedure	NB3W800LMNGEVB_TEST_PROCEDURE.pdf (671kB)
NB3W800LMNGEVB User's Manual	NB3W800LMNGEVB_USERS_MANUAL.pdf (1062kB)

Evaluation/Development Tool Information

Product	Status	Compliance	Short Description
NB3W800LMNGEVB	Active	Pb-free	3.3 V 100/133 MHz Differential 1:8 HCSLCompatible Push-Pull Clock ZDB/Fanout Buffer for PCIe Evaluation Board

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NB3W800LMNG	Active	Pb-free Halide free	QFN-48	485DP	3	Tray JEDEC	490	Contact BDTIC
NB3W800LMNTWG	Active	Pb-free Halide free	QFN-48	485DP	3	Tape and Reel	2500	Contact BDTIC
NB3W800LMNTXG	Active	Pb-free Halide free	QFN-48	485DP	3	Tape and Reel	2500	Contact BDTIC

Specifications

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tskew(o-o) Max (ps)	tR & tF Max (ps)	fmaxClock Typ (MHz)
NB3W800LMNG	Buffer	1	1:8	HCSL	HCSL	3.3	50	87.5	100 133.33
NB3W800LMNTWG	Buffer	1	1:8	HCSL	HCSL	3.3	50	87.5	133.33 100
NB3W800LMNTXG	Buffer	1	1:8	HCSL	HCSL	3.3	50	87.5	100 133.33