NB4N121K: Clock Fanout Buffer, 1:21 Differential, 3.3 V, with HCSL Level Output
The NB4N121K is a Clock differential input fanout distribution 1 to 21 HCSL level differential outputs, optimized for ultra low propagation delay variation. The NB4N121K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 ohm on die termination resistors.
Features- Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and400 MHz
- <1 ps RMS Additive Clock jitter
- Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
- 340 ps Typical Rise and Fall Times
- 800 ps Typical Propagation Delay tPD 100 ps Maximum Propagation
- Delta tPD 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
- Differential HCSL Output Level (700 mV Peak-to-Peak)
| Benefits- Meets wide range of FBDIMM bus frequencies
- Best in class for jitter performance
- Ensures operation in the majority of designs
|
Applications- FBDIMM Clock Distribution
- PCIe I, II, II
- Networking
- Clock Distribution
- High End Computing
| End Products- FBDIMM Memory Support
- Servers
- Routers
|
Simulation Models (1)
Package Drawings (1)
Data Sheets (1)
Evaluation Board Documents (1)
Evaluation/Development Tool Information
| Product | Status | Compliance | Short Description |
|---|
| NB4N121KMNGEVB | Active | Pb-free | Fanout Distribution Evaluation Board |
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| NB4N121KMNG | Active | Pb-free
Halide free | QFN-52 | 485M | 1 | Tray JEDEC | 260 | Contact BDTIC |
| NB4N121KMNR2G | Active | Pb-free
Halide free | QFN-52 | 485M | 1 | Tape and Reel | 2000 | Contact BDTIC |
Specifications
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB4N121KMNG | Buffer | 1 | 1:21 | ECL
TTL
CMOS
CML
LVDS | HCSL | 3.3 | 1 | 50 | 0.8 | 700 | 200 | |
| NB4N121KMNR2G | Buffer | 1 | 1:21 | TTL
CML
ECL
LVDS
CMOS | HCSL | 3.3 | 1 | 50 | 0.8 | 700 | 200 | |
