NB4N316M: AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis

The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The CML outputs are 16 mA open collector which require a resistor load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. The differential outputs produce Current Mode Logic (CML) compatible levels when the receiver is loaded with 50-ohm or 25-ohm loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors. The NB4N316M features an input threshold of approximately 25mV, providibg increased noise immunity and stability. The device is offered in a small 8-pin TSSOP package (MSOP-8 compatible).

Features
  • Maximum Input Clock Frequency > 2.0 GHz
  • Maximum Input Data Rate > 2.5 Gb/s
  • Typically 1 ps of RMS Clock Jitter
  • Typically 10 ps of Data Dependent Jitter
  • 550 ps Typical Propagation Delay
  • 150 ps Typical Rise and Fall Times
  • Differential Open Collector CML Outputs
Applications
  • Signal interface translation for Networking and ATE
  • High Speed CLOCK Applications
Application Notes (6)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s DataNB4N316M/D (153kB)6
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NB4N316MNB4N316M.IBS (20.0kB)1
Package Drawings (1)
Document TitleDocument ID/SizeRevision
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB4N316MDTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
NB4N316MDTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB4N316MDTGSignal Driver11:1LVDS TTL ECL CML HSTL CMOSCML3.31200.5530020002500
NB4N316MDTR2GSignal Driver11:1TTL CML ECL CMOS HSTL LVDSCML3.31200.5530020002500
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data (153kB) NB4N316M
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
IBIS Model for NB4N316M NB4N316M
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L