NB7L11M: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V, with CML Outputs and Internal Termination

The NB7L11M is a differential 1-to-2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively.Inputs incorporate internal 50 Ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Differential 16mA CML (Current Mode Logic) output provides matching 50 Ohm terminations, and 400 mV output swings when externally terminated, 50 Ohm to VCC.

Features
  • Maximum Input Clock up to 8 GHz Typical
  • Maximum Input Data Rate up to 12Gb/s Typical
  • < 0.5 ps of RMS Clock Jitter
  • < 10 ps of Data Dependent Jitter
  • 30 ps Typical Rise and Fall Times
  • 110 ps Typical Propogation Delay
  • 3 ps Typical Within Device Skew
  • Operatiing Range: VCC = 2.375V to 3.465V with VEE = 0V
  • CML Output Level (400 mV Peak-to-Peak Output) Differential Output Only
  • 50 Ω Internal Input and Output Termination Resistors
  • Functionally Compatible with Existing 2.5V / 3.3V LVEL,LVEP, EP, and SG DEvices
  • Pb-Free Packages are Available
Applications
  • OC-48 & OC-192 SONET/SDH data routing
  • Serial Digital HDTV Video Routing
  • ATE High Speed Data Communications Links
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V / 3.3 V 12 Gb/s Differential 1:2 Clock/Data Fan-out Buffer/Translator with CML Outputs & Internal Termination ResistorsNB7L11M/D (223kB)4Aug, 2016
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nb7l11m 3.3VNB7L11M.IBS (20.0kB)1
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB7L11MMNGActivePb-free Halide freeQFN-16485G-011Tube123Contact BDTIC
NB7L11MMNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB7L11MMNGBuffer11:2CML TTL LVDS CMOS ECLCML3.3 2.50.2150.1160800012000
NB7L11MMNR2GBuffer11:2CML CMOS LVDS ECL TTLCML3.3 2.50.2150.1160800012000
2.5 V / 3.3 V 12 Gb/s Differential 1:2 Clock/Data Fan-out Buffer/Translator with CML Outputs & Internal Termination Resistors (223kB) NB7L11M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for nb7l11m 3.3V NB7L11M
QFN16, 3x3, 0.5P NLSF308
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