NB7L14M: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V, 1:4 Differential, 12 Gbps, with CML Outputs and Internal Termination

The NB7L14M is a differential 1-to-4 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively.Inputs incorporate internal 50 Ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Differential 16mA CML (Current Mode Logic) output provides matching 50 Ohm terminations, and 400 mV output swings when externally terminated, 50 Ohm to VCC.

Features

Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12Gb/s Typical
< 0.5 ps Maximum RMS Clock Jitter
< 10 ps Data Dependant Jitter
30 ps Typical Rise & Fall Times
110 ps Typical Propagation Delay
6 ps Typical Within Device Skew
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV Peak-to-Peak Output)Differential Output Only
50Ω Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP, EP, and SG Devices
Pb-Free Packages are Available

Applications

SDH/SONET OC-3 to OC-48 Data Buffering
High Speed Precision Edge Clocking

Application Notes (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure	AND8173/D (144.0kB)	3
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

Package Drawings (1)

Document Title	Document ID/Size	Revision
QFN16, 3x3, 0.5P	485G-01 (57.3kB)	F

Simulation Models (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for nb7l14m 3.3V	NB7L14M.IBS (21.0kB)	1

Evaluation Board Documents (1)

Document Title	Document ID/Size	Revision	Revision Date
NB7L14MMNGEVB Manual	EVBUM2084/D (163.0kB)	2

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5V/3.3V, 10Gb/s Differential 1:4 Clock/Data Fanout Buffer/Translator with CML Outputs and Internal Termination	NB7L14M/D (207.0kB)	6

Evaluation/Development Tool Information

Product	Status	Compliance	Short Description
NB7L14MMNGEVB	Active	Pb-free	Differential Clock Evaluation Board

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NB7L14MMNG	Active	Pb-free Halide free	QFN-16	485G-01	1	Tube	123	Contact BDTIC
NB7L14MMNR2G	Active	Pb-free Halide free	QFN-16	485G-01	1	Tape and Reel	3000	Contact BDTIC