NBSG14: SiGe Clock / Data Fanout Buffer, 1:4 Differential, 2.5 V / 3.3 V, with RSECL Outputs

The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for ultra-low skew and jitter.Inputs incorporate internal 50-ohm termination resistors and acceptNECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.

Features
  • Maximum Input Clock Frequency up to 12 GHz
  • Maximum Input Data Rate up to 12 Gb/s Typical
  • 50 Ω Internal Input Termination Resistors
  • 30 ps Typical Rise and Fall Times
  • 125 ps Typical Propagation Delay
  • RSPECL Output with Operating Range: V = 2.375 V to 3.465 V with VEE = 0 V
  • RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • RSECL Output Level (400 mV Peak-to-Peak Output),
  • Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
End Products
  • ATE Instrumentation, Networking
Application Notes (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Considerations for FCBGA PackagesAND8075/D (56.0kB)0
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Chips that RipAND8068/D (25.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V/3.3 V SiGe Differential 1:4 Clock/Data Driver with RSECL OutputsNBSG14/D (391kB)17Jun, 2014
Simulation Models (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for NBSG14MN 3.3 VNBSG14MN_33V.IBS (9.0kB)2
IBIS Model for nbsg14mn 2.5VNBSG14MN_25V.IBS (9.0kB)2
IBS Model for NBSG14BA (2.5 V)NBSG14BA_25V.IBS (9.0kB)2
IBS Model for NBSG14BA (3.3 V)NBSG14BA_33V.IBS (9.0kB)4
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NBSG14MNGActivePb-free Halide freeQFN-16485G-011Tube123Contact BDTIC
NBSG14MNHTBGActivePb-free Halide freeQFN-16485G-011Tape and Reel100Contact BDTIC
NBSG14MNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NBSG14MNGBuffer11:4CML LVDS TTL CMOS ECLECL2.5 3.30.2150.125551200012000
NBSG14MNHTBGBuffer11:4LVDS TTL CML CMOS ECLECL2.5 3.30.2150.125551200012000
NBSG14MNR2GBuffer11:4LVDS TTL ECL CML CMOSECL3.3 2.50.2150.125551200012000
2.5 V/3.3 V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs (391kB) NBSG14
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Considerations for FCBGA Packages NBSG86A
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Chips that Rip NBSG86A
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for NBSG14MN 3.3 V NBSG14
IBIS Model for nbsg14mn 2.5V NBSG14
IBS Model for NBSG14BA (2.5 V) NBSG14
IBS Model for NBSG14BA (3.3 V) NBSG14
QFN16, 3x3, 0.5P NLSF308