NBSG86A: SiGe Differential Smart Gate, 2.5 V / 3.3 V, with Output Level Select

The NBSG86A is a multi-function differential Logic Gate which can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1 MUX. This device is part of the GigaComm family of high performance Silicon Germanium products. The device is housed in a low profile 4x4 mm, 16-pin, flip-chip BGA or a 3x3 mm 16 pin QFN package.Differential inputs incorporate internal 50-ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps.The NBSG86A employs input clamping circuitry so that under open input conditions (Dx, Dbarx, VTDx, VTDbarx, VTSEL) the outputs of the device will remain stable.

Features

Maximum Input Clock Frequency > 8 GHz Typical
Maximum Data Input Rate > 8 Gb/s Typical
165 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
50Ω Internal Input Termination Resistors
Selectable Output Level Select (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output)

End Products

ATE Instrumentation, Networking

Application Notes (13)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Considerations for FCBGA Packages	AND8075/D (56.0kB)	0
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Chips that Rip	AND8068/D (25.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

Data Sheets (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5V/3.3V SiGe Differential Smart Gate with Output Select	NBSG86A/D (131kB)	19	Jun, 2014

Simulation Models (3)

Document Title	Document ID/Size	Revision
IBIS Model for NBSG86AMN 3.3V 800 mV swing	NBSG86AMN_33_800.IBS (18.0kB)	2
IBS Model for NBSG86ABA (3.3 V, 400 mV)	NBSG86ABA_33V_400MV.IBS - 16.0 (15.0kB)	2
IBS Model for NBSG86ABA (3.3V, 400 mV)	NBSG86ABA_33V_800MV.IBS - 16.0 (17.0kB)	2

Package Drawings (1)

Document Title	Document ID/Size	Revision
QFN16, 3x3, 0.5P	485G-01 (57.3kB)	F

Order Information

Product	Status	Compliance	Package		MSL*	Container		Budgetary Price/Unit
NBSG86AMNG	Active	Pb-free Halide free	QFN-16	485G-01	1	Tube	123	Contact BDTIC
NBSG86AMNHTBG	Active	Pb-free Halide free	QFN-16	485G-01	1	Tape and Reel	100	Contact BDTIC
NBSG86AMNR2G	Active	Pb-free Halide free	QFN-16	485G-01	1	Tape and Reel	3000	Contact BDTIC

Specifications

Product	Type	Channels	Input Level	Output Level	VCC Typ (V)	fToggle Max (MHz)	tpd Typ (ns)	tJitter Typ (ps)	tR & tF Max (ps)
NBSG86AMNG	SmartGate	1	TTL CMOS LVDS CML ECL	RSECL	3.3 2.5	8000	0.165	0.5	65
NBSG86AMNHTBG	SmartGate	1	TTL CMOS LVDS ECL CML	RSECL	3.3 2.5	8000	0.165	0.5	65
NBSG86AMNR2G	SmartGate	1	LVDS CML TTL CMOS ECL	RSECL	2.5 3.3	8000	0.165	0.5	65