TMS320C6713B Floating-Point Digital Signal Processor TMS320C6713B
TMS320C6713, TMS320C6713B DSPs Silicon Errata (Silicon Revisions 2.0, 1.1) TMS320C6713B
Introduction to TMS320C6000 DSP Optimization SMV320C6727B-SP
Thermal Considerations for the DM64xx, DM64x, and C6000 Devices SMV320C6727B-SP
Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B TMS320C6713B
TMS320C6711D, C6712D, C6713B Power Consumption Summary TMS320C6711D
TMS320C621x/671x EDMA Performance Data TMS320C6711D
TMS320C6000 EDMA IO Scheduling and Performance TMS320C6711D
TMS320C621x/TMS320C671x EDMA Architecture TMS320C6711D
TMS320C6000 DSP Peripherals Overview Reference Guide TMS320C6201
TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide TMS320C6713B
TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide TMS320C6201
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide TMS320C6713B
TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide TMS320C6201
TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide TMS320C6711D
TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide SMV320C6727B-SP
TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide TMS320C6201
TMS320C6000 DSP Power-Down Logic and Modes Reference Guide TMS320C6201
TMS320C6000 DSP 32-bit Timer Reference Guide TMS320C6201
TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG TMS320C6711D
TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide TMS320C6711D
TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide TMS320C6711D
“Get smart” with TI’s embedded analytics technology TMS320C6201
Software and Hardware Design Challenges Due to Dynamic Raw NAND Market TMS320C6201
C6713B GDP BSDL Model TMS320C6713B
C6713B PYP IBIS Model (Rev. B) TMS320C6713B
C6713B PYP IBIS Model (Rev. B) TMS320C6713B
C6713B GDP IBIS Model (Rev. B) TMS320C6713B
C6713B GDP IBIS Model (Rev. B) TMS320C6713B
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