MC100EP16: Differential Driver / Receiver

The EP16 is a world-class differential receiver/driver. The device is functionally equivalent to the EL16 and LVEL16 devices with higher performance capabilities. With output transition times significantly faster than the EL16 and LVEL16, the EP16 is ideally suited for interfacing with high frequency sources. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Under open input conditions (pulled to VEE ) internal input clamps will force the Q output LOW. The 100 Series contains temperature compensation.

特性
  • 220 ps Propagation Delay
  • Maximum Frequency > 4 GHz Typical (See Graph)
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output Will Default LOW with Inputs Open or at VEE
  • VBB Output
应用
  • ATE Automatic Test Equipment
封装
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
A Comparison of Key Parametrics of CMOS and Bipolar Integrated Circuits In Line Driver ApplicationsAND8060/D (35.0kB)0
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Differential Receiver/DriverMC10EP16/D (188kB)7Aug, 2016
仿真模型 (4)
Document TitleDocument ID/SizeRevisionRevision Date
IBS Model for MC100EP16DT 3.3VMC100EP16DT_33.IBS (5.0kB)2
IBIS Model for mc100ep16d 5.0VMC100EP16D_50.IBS (5.0kB)2
IBIS Model for mc100ep16d at VEE -5.2MC100EP16D_-52.IBS (5.0kB)1
IBIS Model for mc100ep16dt 5.0VMC100EP16DT_50.IBS (5.0kB)2
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC100EP16DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100EP16DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100EP16DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100EP16DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100EP16MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP16DGSignal Driver11:1CML ECLECL3.3 50.2200.221704000
MC100EP16DR2GSignal Driver11:1CML ECLECL5 3.30.2200.221704000
MC100EP16DTGSignal Driver11:1CML ECLECL3.3 50.2200.221704000
MC100EP16DTR2GSignal Driver11:1CML ECLECL3.3 50.2200.221704000
MC100EP16MNR4GSignal Driver11:1ECL CMLECL3.3 50.2200.221704000
3.3 V / 5 V ECL Differential Receiver/Driver (188kB) MC10EP16
A Comparison of Key Parametrics of CMOS and Bipolar Integrated Circuits In Line Driver Applications MC100EP16
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBS Model for MC100EP16DT 3.3V MC100EP16VT
IBIS Model for mc100ep16d 5.0V MC100EP16VT
IBIS Model for mc100ep16d at VEE -5.2 MC100EP16
IBIS Model for mc100ep16dt 5.0V MC100EP16VT
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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