MC100EP16VC: Differential Driver / Receiver with High Gain and Enable Output

The EP16VC is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output.The EP16VC provides an ENbar input which is synchronized with the data input (D) signal in a way that provides litchless gating of the QHG and QHGbar outputs.When the ENbar signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and ENbar goes HIGH, it will force the QHG LOW and the QHGbar HIGH on the next negative transition of the data input. If the data input is LOW when the ENbar goes HIGH, the next data transition to a HIGH is ignored and QHG remains LOW and QHGbar remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The QHG and QHGbar outputs remain in their disabled state as long as the ENbar input is held HIGH or LOW. The ENbar input has no influence on the Qbar output and the data input is passed on (inverted) to this output whether ENbar is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.

特性
  • 310 ps Typical Prop Delay Qbar, 380 ps Typical Prop Delay QHG, QHGbar
  • Gain > 200
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = –3.0 V to –5.5 V
  • Open Input Default State
  • QHG Output Will Default LOW with D inputs Open or at VEE
  • VBB Output
应用
  • Crystal Oscillators
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V / 5 V ECL Differential Receiver/Driver with High Gain and Enable OutputMC100EP16VC/D (181kB)8Aug, 2016
仿真模型 (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBS Model for MC100EP16DT 3.3VMC100EP16DT_33.IBS (5.0kB)2
IBIS Model for mc100ep16d 5.0VMC100EP16D_50.IBS (5.0kB)2
IBIS Model for mc100ep16dt 5.0VMC100EP16DT_50.IBS (5.0kB)2
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EP16VCDGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100EP16VCDR2GLifetimePb-free Halide freeSOIC-8751-071Tape and Reel2500
MC100EP16VCDTGLast ShipmentsPb-free Halide freeTSSOP-8948R-023Tube100
MC100EP16VCDTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100EP16VCMNR4GLifetimePb-free Halide freeDFN-8506AA1Tape and Reel1000
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100EP16VCDGSignal Driver11:2ECLECL5 3.30.2200.384003000
MC100EP16VCDTR2GSignal Driver11:2ECLECL5 3.30.2200.384003000
3.3 V / 5 V ECL Differential Receiver/Driver with High Gain and Enable Output (181kB) MC100EP16VC
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBS Model for MC100EP16DT 3.3V MC100EP16VT
IBIS Model for mc100ep16d 5.0V MC100EP16VT
IBIS Model for mc100ep16dt 5.0V MC100EP16VT
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220