MC100EP16VT: Differential Driver / Receiver with Variable Output Swing and Internal Input Termination

The MC100EP16VT is a differential receiver functionally equivalent to the 100EP16 with input pins controlling the amplitude of the outputs (pin 1) and providing an internal termination network (pin 4).The VCTRL input pin controls the output amplitude of the EP16VT and is referenced to VCC. The operational range of the VCTRL input is from ≤ VBB (a supply at VCC -1.42 V, maximum output amplitude) to VCC (minimum output amplitude). VBB is an externally supplied voltage equal to VCC -1.42 V. A variable resistor between VCC and VBB, with the wiper driving VCTRL, can control the output amplitude. Typical application circuits and a VCTRL Voltage vs. Output Amplitude graph are described in this data sheet. When left open, the VCTRL pin will be internally pulled down to VEE and operate as a standard EP16, with 100% output amplitude.The VTT input pin offers an internal termination network for a 50 line impedance environment. For further reference, see Application Note AND8020, Termination of ECL Logic Devices. Input considerations are required for D and Dbar under no signal conditions to prevent instability.Special considerations are required for differential inputs under No Signal conditions to prevent instability.

特性

220 ps Propagation Delay
Maximum Frequency > 4 GHz Typical
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range:VCC= 3.0 V to 5.5 V with VEE= 0 V
NECL Mode Operating Range:VCC= 0 V with VEE= -3.0 V to -5.5 V
Open Input Default State
50Ω Internal Termination Resistor
Pb-Free Packages are Available

应用

Free Running Crystal Oscillators

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V / 5 V ECL Differential Receiver/Driver with Variable Output Swing and Internal Input Termination	MC100EP16VT/D (193kB)	5	Aug, 2016

仿真模型 (3)

Document Title	Document ID/Size	Revision
IBS Model for MC100EP16DT 3.3V	MC100EP16DT_33.IBS (5.0kB)	2
IBIS Model for mc100ep16d 5.0V	MC100EP16D_50.IBS (5.0kB)	2
IBIS Model for mc100ep16dt 5.0V	MC100EP16DT_50.IBS (5.0kB)	2

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP16VTDG	Lifetime	Pb-free Halide free	SOIC-8	751-07	1	Tube	98
MC100EP16VTDR2G	Lifetime	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500
MC100EP16VTDTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EP16VTDTR2G	Lifetime	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500
MC100EP16VTMNR4G	Lifetime	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000