MC100EP17: Quad Differential Driver / Receiver
The MC10/100EP17 is a 4-bit differential line receiver based on the EP16 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. Inputs of unused gates can be left open and will not affect the operation of the rest of the device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.
特性
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应用
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封装
应用注释 (15)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
| Designing with PECL (ECL at +5.0 V) | AN1406/D (105.0kB) | 2 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| ECLinPS Plus™ Spice Modeling Kit | AND8009/D (343.0kB) | 11 | |
| ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide | AND8002 (71kB) | 12 | |
| Interfacing Between LVDS and ECL | AN1568/D (121.0kB) | 11 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Phase Lock Loop General Operations | AND8040/D (64.0kB) | 3 | |
| Storage and Handling of Drypack Surface Mount Device | AND8003/D (49kB) | 2 | Mar, 2016 |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 | |
| Thermal Analysis and Reliability of WIRE BONDED ECL | AND8072/D (119.0kB) | 5 | |
| Using Wire-OR Ties in ECLInPS™ Designs | AN1650/D (1130.0kB) | 3 |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3 V/5 V ECL Quad Differential Driver/Receiver | MC10EP17/D (120kB) | 10 | Dec, 2016 |
仿真模型 (2)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for mc100ep17dt 3.3V | MC100EP17DT_33.IBS (7.0kB) | 1 | |
| IBIS Model for mc100ep17dt at -5.2 VEE | MC100EP17DT_-52.IBS (7.0kB) | 1 |
封装图纸 (3)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| QFN20, 4x4, 0.5P | 485E-01 (60.9kB) | B |
| SOIC-20 WB | 751D-05 (36.3kB) | H |
| TSSOP-20 WB | 948E-02 (39.7kB) | D |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100EP17DTG | Active | Pb-free Halide free | TSSOP-20 | 948E-02 | 1 | Tube | 75 | 联系BDTIC |
| MC100EP17DTR2G | Lifetime | Pb-free Halide free | TSSOP-20 | 948E-02 | 1 | Tape and Reel | 2500 | |
| MC100EP17DWG | Active | Pb-free Halide free | SOIC-20W | 751D-05 | 3 | Tube | 38 | 联系BDTIC |
| MC100EP17DWR2G | Lifetime | Pb-free Halide free | SOIC-20W | 751D-05 | 3 | Tape and Reel | 1000 | |
| MC100EP17MNG | Last Shipments | Pb-free Halide free | QFN-20 | 485E-01 | 1 | Tube | 92 | |
| MC100EP17MNTXG | Last Shipments | Pb-free Halide free | QFN-20 | 485E-01 | 1 | Tape and Reel | 3000 | |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MC100EP17DTG | Signal Driver | 4 | 1:1 | ECL CML | ECL | 5 3.3 | 0.147 | 0.22 | 220 | 3000 | ||
| MC100EP17DWG | Signal Driver | 4 | 1:1 | CML ECL | ECL | 5 3.3 | 0.147 | 0.22 | 220 | 3000 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for mc100ep17dt 3.3V MC100EP17
- IBIS Model for mc100ep17dt at -5.2 VEE MC100EP17
- TSSOP-20 WB NLSX3018
- SOIC-20 WB NLSX3018
- QFN20, 4x4, 0.5P MC10EP57
