MC100EP91: PECL to NECL Translator _ BDTIC 中国领先电子元器件代理商

MC100EP91: PECL to NECL Translator

The MC100EP91 is a triple AnyLevel™ positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL output signals. VEE at -3.0 V to -5.5 V.

特性

Maximum Input Clock Frequency > 2.0 GHz Typical
Maximum Input Data Rate > 2.0 Gb/s Typical
500 ps Typical Propagation Delay
Operating Range: VCC = 2.375 V to 3.8 V; VEE = 3.0 V to 5.5 V; GND = 0 V
Q Output will Default LOW with Inputs Open or at GND

应用

General Purpose Data and Clock Level Translation

应用注释 (10)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL	MC100EP91/D (175kB)	6	Aug, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for MC100EP91DW with VCC at 3.3 V and VEE at -3.3 V	MC100EP91DW_33-33.IBS (6.0kB)	0

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN24, 4x4, 0.5P	485L-01 (60.0kB)	B
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EP91DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
MC100EP91DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC
MC100EP91MNG	Active	Pb-free Halide free	QFN-24	485L-01	1	Tube	92	联系BDTIC
MC100EP91MNR2G	Active	Pb-free Halide free	QFN-24	485L-01	1	Tape and Reel	3000	联系BDTIC

订购产品技术参数

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EP91DWG	3	CML ECL LVDS CMOS TTL	ECL	3.3	2	0.5	250
MC100EP91DWR2G	3	ECL TTL LVDS CMOS CML	ECL	3.3	2	0.5	250
MC100EP91MNG	3	CML TTL LVDS ECL CMOS	ECL	3.3	2	0.5	250
MC100EP91MNR2G	3	ECL LVDS CMOS TTL CML	ECL	3.3	2	0.5	250

Datasheet: 2.5 V / 3.3 V Any Level Positive Input to -3.3 V/-5.5 V NECL (175kB) MC100EP91














Other: QFN24, 4x4, 0.5P NCN8026; SOIC-20 WB NLSX3018; ECL Clock Distribution Techniques NB100LVEP91; Designing with PECL (ECL at +5.0 V) NB100LVEP91; ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91; Metastability and the ECLinPS Family MC10EPT20; Interfacing Between LVDS and ECL NB100ELT23L; Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201; Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91; Termination of ECL Logic Devices NB100LVEP91; Interfacing with ECLinPS NB100LVEP91; AC Characteristics of ECL Devices NB100LVEP91; IBIS Model for MC100EP91DW with VCC at 3.3 V and VEE at -3.3 V MC100EP91