MC100EPT622: Translator, 10-bit LVTTL / LVCMOS to LVPECL

The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required. The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel-to-channel skew.

特性
  • 450 ps Typical Propogation Delay
  • Maximum Frequency > 1.5 GHz Typical
  • PECL Mode
  • Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
  • PNP LVTTL Inputs for Minimal Loading
  • Q Outputs Will Default HIGH with Inputs Open
  • The 100 Series Contains Temperature Compensation
封装
应用注释 (9)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN32, 5x5, 0.5P, 3.1x3.1EP488AM (57.4kB)A
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, 10-bit LVTTL / LVCMOS to LVPECLMC100EPT622/D (131.0kB)6
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC100EPT622FAGActivePb-free Halide freeLQFP-32联系BDTIC2Tray JEDEC250联系BDTIC
MC100EPT622FAR2GActivePb-free Halide freeLQFP-32联系BDTIC2Tape and Reel2000联系BDTIC
MC100EPT622MNGActivePb-free Halide freeQFN-32488AM1Tube74联系BDTIC
MC100EPT622MNR4GLifetimePb-free Halide freeQFN-32488AM1Tape and Reel1000
订购产品技术参数
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EPT622FAG10CMOS TTLECL3.315000.5450
MC100EPT622FAR2G10CMOS TTLECL3.315000.5450
MC100EPT622MNG10TTL CMOSECL3.315000.5450
Datasheet
Translator, 10-bit LVTTL / LVCMOS to LVPECL (131.0kB) MC100EPT622
Other
QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804
ECL Clock Distribution Techniques NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
The ECL Translator Guide NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Termination of ECL Logic Devices NB100LVEP91
Interfacing with ECLinPS NB100LVEP91
AC Characteristics of ECL Devices NB100LVEP91