MC100H643: 1:8 Clock Driver

The MC10H/100H643 is a dual supply, low skew translating 1:8 clock driver. Devices in the H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The dual-supply H643 is similar to the H641, which is a single-supply 1:9 version of the same function. The device features a 48mA TTL output stage, with AC performance specified into a 50pF load capacitance. A Latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

特性
  • ECL/TTL Version of Popular ECLinPS™ E111
  • Low Skew Within Device 0.5ns
  • Guaranteed Skew Spec Part-to-Part 1.0ns
  • Latch
  • Differential Internal Design
  • VBB Output
  • Dual Supply
  • Reset/Enable
  • Multiple TTL and ECL Power/Ground Pins
  • Pb-Free Packages are Available
应用注释 (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (66kB)11
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Dual Supply ECL-TTL 1:8 Clock DriverMC10H643/D (113.0kB)8
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100H643FNMC100H643FN.IBS (12.0kB)0
封装图纸 (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价）
MC100H643FNGActivePb-free Halide free1:8 Clock DriverPLCC-28776-023Tube37联系BDTIC
MC100H643FNR2GActivePb-free Halide free1:8 Clock DriverPLCC-28776-023Tape and Reel500联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100H643FNGBuffer11:8ECLTTL55004.6120080
MC100H643FNR2GBuffer11:8ECLTTL55004.6120080
Dual Supply ECL to TTL 1:8 Clock Driver (133kB) MC10H643
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for MC100H643FN MC100H643
28 LEAD PLCC MC10H604
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