MC100LVEL01: ECL 4-Input OR/NOR Gate _ BDTIC 中国领先电子元器件代理商

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MC100LVEL01: ECL 4-Input OR/NOR Gate

The MC100LVEL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a -3.3V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in AC performance.

特性

370ps Propagation Delay
High Bandwidth Output Transitions
ESD Protection: >2 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with All Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 83 devices
Pb-Free Packages are Available

应用注释 (15)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (66kB)	11
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (66kB)	11
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS™	AND8066/D (58.0kB)	2
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (106.0kB)	1
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V ECL 4-Input OR/NOR Gate	MC100LVEL01/D (124.0kB)	4

仿真模型 (3)

Document Title	Document ID/Size	Revision
IBIS Model for mc100lvel01d 3.3V	MC100LVEL01D_33.IBS (5.0kB)	1
IBIS Model for mc100lvel01dt 3.3V	MC100LVEL01DT_33.IBS (5.0kB)	4
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	具体说明	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100LVEL01DG	Active	Pb-free Halide free	ECL 4-Input OR/NOR Gate	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100LVEL01DR2G	Active	Pb-free Halide free	ECL 4-Input OR/NOR Gate	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100LVEL01DTG	Active	Pb-free Halide free	ECL 4-Input OR/NOR Gate	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100LVEL01DTR2G	Active	Pb-free Halide free	ECL 4-Input OR/NOR Gate	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input Level	Output Level	VCC Typ (V)	fToggle Max (MHz)	tpd Typ (ns)	tJitter Typ (ps)	tR & tF Max (ps)
MC100LVEL01DG	OR/NOR	1	ECL	ECL	3.3	2000	0.37	1	320
MC100LVEL01DR2G	OR/NOR	1	ECL	ECL	3.3	2000	0.37	1	320
MC100LVEL01DTG	OR/NOR	1	ECL	ECL	3.3	2000	0.37	1	320
MC100LVEL01DTR2G	OR/NOR	1	ECL	ECL	3.3	2000	0.37	1	320