MC10E143: 5.0 V ECL 9-Bit Hold Register

The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0-D8 accepting parallel input data. The SEL (Select) input pin is used to switch between the two modes of operation HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.The 100 Series contains temperature compensation.

特性
  • 700MHz Min. Operating Frequency
  • 9-Bit for Byte-Parity Applications
  • Asynchronous Master Reset
  • Dual Clocks
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • 75kW Input Pulldown Resistors
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 2 KV HBM, > 200 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 484 devices
  • Pb-Free Packages are Available
封装
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS™ Circuit Performance at Non-Standard VIH LevelsAN1404/D (51.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
5 V ECL 9-Bit Hold RegisterMC10E143/D (151kB)8Jul, 2016
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10E143FNMC10E143FN.IBS (11.0kB)
封装图纸 (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10E143FNR2GActivePb-free Halide freePLCC-28776-023Tape and Reel500联系BDTIC
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10E143FNR2GRegister9ECLECL510.80.050.30.7800
Datasheet
5 V ECL 9-Bit Hold Register (151kB) MC10E143
Other
28 LEAD PLCC MC10H604
ECLinPS™ Circuit Performance at Non-Standard VIH Levels MC10E195
ECL Clock Distribution Techniques NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
Metastability and the ECLinPS Family MC10EPT20
Interfacing Between LVDS and ECL NB100ELT23L
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
The ECL Translator Guide NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
Phase Lock Loop General Operations MC10H604
Interfacing with ECLinPS NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
AC Characteristics of ECL Devices NB100LVEP91
IBIS Model for MC10E143FN MC10E143
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604