MC10E155: ECL 6-Bit 2:1 Mux Latch _ BDTIC 中国领先电子元器件代理商

首页 > ON 安森美 > 时钟及数据分配 > 多工器及交点开关 > MC10E155

MC10E155: ECL 6-Bit 2:1 Mux Latch

The MC10E/100E155 contains six 2:1 multiplexers followed by transparent latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.The 100 Series contains temperature compensation.

特性

850ps Max. LEN to Output
825ps Max. D to Output
Single-Ended Outputs
Asynchronous Master Reset
Dual Latch-Enables
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
Internal Input Pulldown Resistors
ESD Protection: > 2 kV HBM, > 200 V MM
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 239 devices
Pb-Free Packages are Available

应用注释 (17)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (66kB)	11
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit	AN1503/D (120.0kB)	6
ECLinPS™ Circuit Performance at Non-Standard VIH Levels	AN1404/D (51.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS™	AND8066/D (58.0kB)	2
Metastability and the ECLinPS Family	AN1504/D (103.0kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (106.0kB)	1
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

封装图纸 (1)

Document Title	Document ID/Size	Revision
28 LEAD PLCC	776-02 (67.7kB)	F

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
5V ECL 6-Bit 2:1 Mux Latch	MC10E155/D (126.0kB)	8

产品订购型号

产品	状况	Compliance	具体说明	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10E155FNG	Active	Pb-free Halide free	ECL 6-Bit 2:1 Mux Latch	PLCC-28	776-02	3	Tube	37	联系BDTIC
MC10E155FNR2G	Active	Pb-free Halide free	ECL 6-Bit 2:1 Mux Latch	PLCC-28	776-02	3	Tape and Reel	500	联系BDTIC