MC10EL11: Clock / Data Fanout Buffer, 1:2 Differential, ECL, 5.0 V
The MC10EL/100EL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the EL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the EL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW.The 100 Series contains temperature compensation.
特性
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封装
应用注释 (17)
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 5 V ECL 1:2 Differential Fanout Buffer | MC10EL11/D (160kB) | 11 | Jul, 2016 |
仿真模型 (4)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for mc10el11d -5.0V | MC10EL11D_-50.IBS (7.0kB) | 1 | |
| IBIS Model for mc10el11d 5.0V | MC10EL11D_50.IBS (16.0kB) | 1 | |
| IBIS Model for mc10el11dt -5.0V | MC10EL11DT_-50.IBS (16.0kB) | 1 | |
| IBIS Model for mc10el11dt 5.0V | MC10EL11DT_50.IBS (16.0kB) | 1 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
| TSSOP 8 3.0x3.0x0.95 mm | 948R-02 (77.3kB) | A |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10EL11DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC10EL11DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
| MC10EL11DTG | Last Shipments | Pb-free Halide free | TSSOP-8 | 948R-02 | 3 | Tube | 100 | |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MC10EL11DG | Buffer | 1 | 1:2 | ECL | ECL | 5 | 0.6 | 20 | 0.265 | 350 | 1500 | |
| MC10EL11DR2G | Buffer | 1 | 1:2 | ECL | ECL | 5 | 0.6 | 20 | 0.265 | 350 | 1500 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for mc10el11d -5.0V MC10EL11
- IBIS Model for mc10el11d 5.0V MC10EL11
- IBIS Model for mc10el11dt -5.0V MC10EL11
- IBIS Model for mc10el11dt 5.0V MC10EL11
- SOIC-8 Narrow Body CM1216
- TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
