MC10EP451: 3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to < VEE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state. The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.The 100 Series contains temperature compensation.

特性

450 ps Typical Propagation Delay
Maximum Frequency > 3.0 GHz Typical
Asynchronous Master Reset
20 ps Skew Within Device, 35 ps Skew Device-To-Device
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available

应用

High Performance Logic for test systems

封装

应用注释 (10)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V ECL 6-Bit Differential Register with Master Reset	MC10EP451/D (108kB)	10

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
ECLinPS Plus SPICE Modeling Kit	AND8009 (343.0kB)	11

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10EP451FAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
MC10EP451FAR2G	Lifetime	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000
MC10EP451MNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	联系BDTIC
MC10EP451MNR4G	Lifetime	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000

订购产品技术参数

Product	Type	Bits	Input Level	Output Level	VCC Typ (V)	tJitter Typ (ps)	tpd Typ (ns)	tsu Min (ns)	th Min (ns)	trec Typ (ns)	tR & tF Max (ps)	fToggle Typ (MHz)
MC10EP451FAG	Register	6	ECL CML	ECL	3.3 5	0.2	0.45	0.08	0.08	0.15	250	3000
MC10EP451MNG	Register	6	CML ECL	ECL	5 3.3	0.2	0.45	0.08	0.08	0.15	250	3000

Datasheet: 3.3V / 5V ECL 6-Bit Differential Register with Master Reset (108kB) MC10EP451













Other: QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804; ECL Clock Distribution Techniques NB100LVEP91; Designing with PECL (ECL at +5.0 V) NB100LVEP91; Interfacing Between LVDS and ECL NB100ELT23L; The ECL Translator Guide NB100LVEP91; Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201; Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91; ECLinPS Plus™ Spice Modeling Kit MC10EPT20; ECLinPS Plus SPICE Modeling Kit NB4N840M; Termination of ECL Logic Devices NB100LVEP91; Interfacing with ECLinPS NB100LVEP91; AC Characteristics of ECL Devices NB100LVEP91