MC10H016: 4-Bit Binary Counter
The MC10H016 is a high-speed synchronous, presettable, cascadable 4-bit binary counter. It is useful for a large number of conversion, counting and digital integration applications.
特性
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封装
应用注释 (10)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
| Designing with PECL (ECL at +5.0 V) | AN1406/D (105.0kB) | 2 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| Family Characteristics for MECL 10H™ and MECL 10K™ | TND309/D (248.0kB) | 1 | |
| Interfacing Between LVDS and ECL | AN1568/D (121.0kB) | 11 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 |
封装图纸 (2)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| 20 LEAD PLLC | 775-02 (60.9kB) | F |
| PDIP-16 | 648-08 (34.2kB) | V |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 4-Bit Binary Counter | MC10H016/D (144kB) | 9 | Aug, 2016 |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10H016FNR2G | Active | Pb-free Halide free | PLLC-20 | 775-02 | 3 | Tape and Reel | 500 | 联系BDTIC |
| MC10H016PG | Active | Pb-free Halide free | PDIP-16 | 648-08 | NA | Tube | 25 | 联系BDTIC |
订购产品技术参数
| Product | Type | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|
| MC10H016FNR2G | Counter | ECL | ECL | -5.2 | 200 | 1.8 | 0.002 |
| MC10H016PG | Counter | ECL | ECL | -5.2 | 200 | 1.8 | 0.002 |
- Datasheet
- 4-Bit Binary Counter (144kB) MC10H016
- Other
- PDIP-16 MC10H350
- 20 LEAD PLLC MC10H351
- ECL Clock Distribution Techniques NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- The ECL Translator Guide NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Termination of ECL Logic Devices NB100LVEP91
- Interfacing with ECLinPS NB100LVEP91
- AC Characteristics of ECL Devices NB100LVEP91
- Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
