MC10H115: Quad Line Receiver

The MC10H115 is a quad differential amplifier designed for use in sensing differential signals over long lines. This 10H part is a functional/ pinout duplication of the standard MECL 10K family part, with 100% improvement in counting frequency and no increase in power-supply current. The base bias supply (VBB) is made available at Pin 9 to make the device useful as a Schmitt trigger, or in other applications where a stable reference voltage is necessary. Active current sources provide the MC10H115 with excellent common mode rejection. If any amplifier in a package is not used, one input of that amplifier must be connected to VBB (Pin 9) to prevent upsetting the current source bias network.

特性
  • Propagation Delay, 1.0 ns Typical
  • Power Dissipation 110 mW Typ/Pkg (No Load)
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K-Compatible
  • Pb-Free Packages are Available
封装
应用注释 (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Quad Line ReceiverMC10H115/D (135kB)8
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10H115FNGActivePb-free Halide freePLLC-20775-023Tube46联系BDTIC
MC10H115FNR2GLast ShipmentsPb-free Halide freePLLC-20775-023Tape and Reel500
MC10H115PGActivePb-free Halide freePDIP-16648-08NATube25联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC10H115FNGSignal Driver41:1ECLECL-5.20.851600
MC10H115PGSignal Driver41:1ECLECL-5.20.851600
Quad Line Receiver (135kB) MC10H115
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
20 LEAD PLLC MC10H351
PDIP-16 MC10H350