MC10H141: 4-Bit Universal Shift Register

The MC10H141 is a four-bit universal shift register. This device is a functional/pinout duplication of the standard MECL 10K part with 100% improvement in propagation delay and operation frequency and no increase in power supply current.

特性
  • Shift frequency, 250 MHz Min
  • Power Dissipation, 425 mW Typical
  • Improved Noise Margin 150 mV (over operating voltage and temperature range)
  • Voltage Compensated
  • MECL 10K Compatible
  • Pb-Free Packages are Available
应用注释 (10)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Four-Bit Universal Shift RegisterMC10H141/D (137kB)9Aug, 2016
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
MC10H141FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500联系BDTIC
MC10H141PGLast ShipmentsPb-free Halide freePDIP-16648-08NATube25
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10H141FNR2GShift Register4ECLECL-5.21.51.512400250
Datasheet
Four-Bit Universal Shift Register (137kB) MC10H141
Other
PDIP-16 MC10H350
20 LEAD PLLC MC10H351
ECL Clock Distribution Techniques NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
The ECL Translator Guide NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Termination of ECL Logic Devices NB100LVEP91
Interfacing with ECLinPS NB100LVEP91
AC Characteristics of ECL Devices NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604