MC10H643: 1:8 Clock Driver _ BDTIC 中国领先电子元器件代理商

MC10H643: 1:8 Clock Driver

The MC10H/100H643 is a dual supply, low skew translating 1:8 clock driver. Devices in the H600 translator series utilize the 28-lead PLCC for optimal power pinning, signal flow through and electrical performance. The dual-supply H643 is similar to the H641, which is a single-supply 1:9 version of the same function. The device features a 48mA TTL output stage, with AC performance specified into a 50pF load capacitance. A Latch is provided on-chip. When LEN is LOW (or left open, in which case it is pulled LOW by the internal pulldowns) the latch is transparent. A HIGH on the enable pin (EN) forces all outputs LOW. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

特性

ECL/TTL Version of Popular ECLinPS™ E111
Low Skew Within Device 0.5ns
Guaranteed Skew Spec Part-to-Part 1.0ns
Latch
Differential Internal Design
VBB Output
Dual Supply
Reset/Enable
Multiple TTL and ECL Power/Ground Pins
Pb-Free Packages are Available

封装

应用注释 (10)

Document Title	Document ID/Size	Revision
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
Family Characteristics for MECL 10H™ and MECL 10K™	TND309/D (248.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12