The NB3L83948C is a pure 2.5 / 3.3 V (VDD = VDDO) or mixed mode 3.3 Core / 2.5 V Output (VDDO) clock distribution buffer with the capability to select either a differential LVPECL / LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL compatible input clock, such as a Primary and a Test Clock. All other control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS level compatible.
特性
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Document Title | Document ID/Size | Revision | Revision Date |
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2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX Input Clock Buffer with 1:12 LVCMOS Fanout | NB3L83948C/D (82kB) | 2 |
Document Title | Document ID/Size | Revision |
---|---|---|
32 LEAD LQFP 7x7, 0.8P | 873A-02 (51.1kB) | C |
产品 | 状况 | Compliance | 具体说明 | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价) | ||
---|---|---|---|---|---|---|---|---|---|
NB3L83948CFAG | Active | Pb-free Halide free | 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX Input Clock Buffer with 1:12 LVCMOS Fanout | LQFP-32 | 873A-02 | 2 | Tray JEDEC | 250 | 联系BDTIC |
NB3L83948CFAR2G | Active | Pb-free Halide free | 2.5 V / 3.3 V Differential and LVTTL/LVCMOS 2:1 MUX Input Clock Buffer with 1:12 LVCMOS Fanout | LQFP-32 | 873A-02 | 2 | Tape and Reel | 2000 | 联系BDTIC |
Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
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NB3L83948CFAG | Buffer | 1 | 2:1:12 | HCSL LVCMOS LVDS LVHSTL LVPECL SSTL | LVCMOS | 2.5 3.3 | 100 | 1000 1300 | 350 | |||
NB3L83948CFAR2G | Buffer | 1 | 2:1:12 | HCSL LVCMOS LVDS LVHSTL LVPECL SSTL | LVCMOS | 2.5 3.3 | 100 | 1000 1300 | 350 |