NB4N527S: Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination

NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.25 GHz, respectively. The NB4N527S has a wide input common mode range of GND+50 mV to VCC-50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components. The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.

特性
  • Maximum Input Clock Frequency up to 1.25 GHz
  • Maximum Input Data Rate up to 2.5 Gb/s
  • 500 ps Maximum Propagation Delay
  • 2 ps Maximum RMS Jitter
  • 300 ps Maximum Rise/Fall Times
  • Single Power Supply; VCC = 3.3 V +/- 10%
  • Temperature Compensated TIA/EIA644 Compliant LVDS Outputs
  • Internal 50 Termination Resistor per Input Pin
  • GND + 50 mV to VCC 50 mV VCMR Range
应用
  • OC-3 to OC-48 SDH/SONET Clock & Data Applications
  • 1 GbE, 1G & 2G Fibrechannel Clock & Data Applications
  • Precision LVDS Clock Buffering & Translation
应用注释 (8)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for nb4n527s.NB4N527S.IBS (23.0kB)1
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB4N527SMNEVB ManualEVBUM2077/D (313.0kB)2
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal TerminationNB4N527S/D (175.0kB)5
评估板与开发工具
产品状况Compliance简短说明
NB4N527SMNEVBActiveTranslator with Internal Termination Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB4N527SMNGActivePb-free Halide freeQFN-16485G-011Tube123联系BDTIC
NB4N527SMNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB4N527SMNGSignal Driver21:1CML CMOS HSTL ECL LVDSLVDS3.30.5250.3714015002500
NB4N527SMNR2GSignal Driver21:1CML ECL HSTL LVDS CMOSLVDS3.30.5250.3714015002500
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination (175.0kB) NB4N527S
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for nb4n527s. NB4N527S
EVBUM2077/D - 313 NB4N527SMNEVB
QFN16, 3x3, 0.5P NLSF308