NB4N855S: Translator, 3.3 V, 1.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer

NB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin-for-pin plug in compatible to the SY55855V in a 3.3 V applications.The NB4N855S has a wide input common mode range of GND + 50 mV to VCC - 50 mV. This feature is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels.The device is offered in a small 10 lead MSOP package. NB4N855S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.

特性
  • Guaranteed Input Clock Frequency up to 1.0 GHz
  • Guaranteed Input Data Rate up to 1.5 Gb/s
  • 490 ps Maximum Propagation Delay
  • 1.0 ps Maximum RMS Jitter
  • 180 ps Maximum Rise/Fall Times
  • Single Power Supply; VCC = 3.3 V ±10%
  • Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs
  • GND + 50 mV to VCC - 50 mV VCMR Range
  • Pb-Free Packages is Available
优势
  • precision edge placement
应用
  • Translation of all major signal types to LVDS in heterogenous systems.
  • Signal driving and reception in communications and networking applications.
终端产品
  • General High Speed LOGIC
应用注释 (8)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
C/O FOR MICRO 10 PKG846B (30.6kB)D
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
ECLinPS Plus SPICE Modeling KitAND8009 (343.0kB)11
IBIS Model for nb4n855sNB4N855S.IBS (23.0kB)3
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB4N855SMEVB ManualEVBUM2079/D (370.0kB)2
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Translator, 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/BufferNB4N855S/D (203.0kB)4
评估板与开发工具
产品状况Compliance简短说明
NB4N855SMEVBActiveTranslator Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB4N855SMR4GActivePb-free Halide freeMicro10846B1Tape and Reel1000联系BDTIC
NB4N855SMR4ObsoleteMicro10846B1Tape and Reel1000
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB4N855SMR4GSignal Driver21:1HSTL SSTL ECL CMOS CML TTL LVDSLVDS3.30.5350.4118015002500
Translator, 3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer (203.0kB) NB4N855S
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
ECLinPS Plus SPICE Modeling Kit NB4N840M
IBIS Model for nb4n855s NB4N855S
EVBUM2079/D - 370 NB4N855SMEVB
C/O FOR MICRO 10 PKG NLAS4717