NB6L56: Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs

The NB6L56 is a high performance Dual 2-to-1 Differential Clock or Data multiplexer. The Multi-Level differential inputs incorporate internal 50 Ohms termination resistors that are accessed through the VT pin. This feature allows the NB6L56 to accept various Differential logic level standards, such as LVPECL, CML or LVDS. Outputs are 800 mV LVPECL signals.

特性

Maximum Input Data Rate > 2.5 Gbps
Maximum Input Clock Frequency > 2.5 GHz
Jitter is < 1 ps RMS RJ (Data); < 10 ps PP DJ (Data); and < 0.7 ps RMS Crosstalk induced jitter (CLOCK)
360 ps Max Propagation Delay
180 ps Max Rise and Fall Times
Operating Range is VCC = 2.5 5% (2.375 V to 2.625 V with VEE = 0 V), orVCC =3.3 10% (3.0 V to 3.6 V with VEE = 0 V)
Internal 50 Input Termination Resistors
Industrial Temp. Range (40C to 85C)
QFN32 Package

应用

Data Communications System
SONET OC-3 to OC-48
Fibre Channel
GigE

终端产品

LAN/WAN
ATE
Test and Measurement
Enterprise Servers

应用注释 (7)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5