NB7L86M: 2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination

The NB7L86M is a multi-function differential Logic Gate, whichcan be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1MUX. This device is part of the GigaComm family of highperformance Silicon Germanium products. The NB7L86M is anultra-low jitter multi-logic gate with a maximum data rate of 12 Gb/sand input clock frequency of 8 GHz suitable for Data CommunicationSystems, Telecom Systems, Fiber Channel, and GigE applications.The device is housed in a low profile 3x3 mm 16-pin QFN package.Differential inputs incorporate internal 50 Ω termination resistorsand accept LVNECL (Negative ECL), LVPECL (Positive ECL),LVCMOS, LVTTL, CML, or LVDS. The differential 16 mA CMLoutput provides matching internal 50 Ω termination, and 400 mVoutput swing when externally terminated 50 Ω to VCC.Application notes, models, and support documentation are availableon www.onsemi.com.

特性

Maximum Input Clock Frequency up to 8 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
30 ps Typical Rise and Fall Times
90 ps Typical Propagation Delay
2 ps Typical Within Device Skew
CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV Peak-to-Peak Output) Differential Output
50 Ω Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices
Pb-Free Packages are Available

应用

Data routing in Data Communication Systems, Telecom Systems, Fiber Channel, and GigE applications.
Clock multiplexing for redundancy

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure	AND8173/D (144.0kB)	3
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V 12 Gb/s Differential Clock/Data Smart Gate (2:1 Mux, AND/NAND, OR/NOR, XOR/XNOR) w/CML Output and Internal Termination	NB7L86M/D (1416.0kB)	7