SN74ALVCH162830 具有三态输出的 20 位缓冲器/驱动器
SN74ALVCH162830 描述
This 1-bit to 2-bit address driver is designed for 1.65-V to 3.6-V VCC operation.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-
resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN74ALVCH162830 | |
| Voltage Nodes(V) | 3.3, 2.7, 2.5, 1.8 |
| Vcc range(V) | 1.65 to 3.6 |
| Logic | True |
| Input Level | LVTTL |
| Output Level | LVTTL |
| Output Drive(mA) | -12/12 |
| No. of Outputs | 36 |
| tpd max(ns) | 3.5 |
| Static Current | 0.04 |
| Rating | Catalog |
| Technology Family | ALVC |
SN74ALVCH162830 特性
- Member of the Texas Instruments Widebus™ Family
- Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74ALVCH162830 应用技术支持与电子电路设计开发资源下载
- SN74ALVCH162830 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
- Semiconductor Packing Methodology (PDF 3005 KB)
- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
