SN74ALVTH162827 具有三态输出的 2.5V/3.3V 20 位缓冲器/驱动器
SN74ALVTH162827 描述
The 'ALVTH162827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\, or 2OE1\ and 2OE2\) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When VCC is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN74ALVTH162827 | |
| Voltage Nodes(V) | 3.3, 2.5 |
| Vcc range(V) | 2.3 to 3.6 |
| Logic | True |
| Input Level | TTL/CMOS |
| Output Level | LVTTL |
| Output Drive(mA) | -12/12 |
| No. of Outputs | 16 |
| tpd max(ns) | 4.1 |
| Static Current | 5 |
| Rating | Catalog |
| Technology Family | ALVTLVT |
SN74ALVTH162827 特性
- State-of-the-Art Advanced BiCMOS Technology (ABT) WidebusTM Design for 2.5-V and 3.3-V Operation and Low Static Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V VCC)
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Power Off Disables Outputs, Permitting Live Insertion
- High-Impedance State During Power Up and Power Down Prevents Driver Conflict
- Uses Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
- Output Ports Have Equivalent 30-
Series Resistors, So No External Resistors Are Required
- Auto3-State Eliminates Bus Current Loading When Output Exceeds VCC + 0.5 V
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model; and Exceeds 1000 V Using Charged-Device Model, Robotic Method
- Flow-Through Architecture Facilitates Printed Circuit Board Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package
SN74ALVTH162827 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74ALVTH162827DL | ACTIVE | -40 to 85 | 1.40 | 1ku | SSOP (DL) | 56 | 25 | TUBE | ALVTH162827 |
| SN74ALVTH162827LR | ACTIVE | -40 to 85 | 1.20 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | ALVTH162827 |
SN74ALVTH162827 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74ALVTH162827DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH162827DL | SN74ALVTH162827DL |
| SN74ALVTH162827LR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ALVTH162827LR | SN74ALVTH162827LR |
SN74ALVTH162827 应用技术支持与电子电路设计开发资源下载
- SN74ALVTH162827 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
- Semiconductor Packing Methodology (PDF 3005 KB)
- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
