The ’LV125A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.
These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down
SN74LV125A | |
Voltage Nodes(V) | 5, 3.3, 2.5 |
Vcc range(V) | 2.0 to 5.5 |
Logic | True |
Input Level | LVTTL |
Output Level | LVTTL |
Output Drive(mA) | -8/8 |
No. of Outputs | 4 |
tpd max(ns) | 9.5 |
Static Current | 0.02 |
Rating | Catalog |
Technology Family | LV-A |
器件 | 状态 | 温度 | 价格(美元) | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
SN74LV125AD | ACTIVE | -40 to 85 | 0.28 | 1ku | SOIC (D) | 14 | 25 | TUBE | LV125A |
SN74LV125ADE4 | ACTIVE | -40 to 85 | 0.28 | 1ku | SOIC (D) | 14 | 25 | TUBE | LV125A |
SN74LV125ADG4 | ACTIVE | -40 to 85 | 0.28 | 1ku | SOIC (D) | 14 | 25 | TUBE | LV125A |
器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
SN74LV125AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV125AD | SN74LV125AD |
SN74LV125ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV125ADE4 | SN74LV125ADE4 |
SN74LV125ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV125ADG4 | SN74LV125ADG4 |