SN74LVC1G126-Q1 汽车类 具有三态输出的单路总线缓冲器闸
SN74LVC1G126-Q1 描述
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G126-Q1 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
SN74LVC1G126-Q1 特性
- Qualified for Automotive Applications
- ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Low Power Consumption, 10-µA Max ICC
- ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
SN74LVC1G126-Q1 应用技术支持与电子电路设计开发资源下载
- SN74LVC1G126-Q1 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
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- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
