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SN74LVC2G125-Q1 汽车类具有三态输出的双路总线缓冲器闸

SN74LVC2G125-Q1 描述

The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down

SN74LVC2G125-Q1 特性

• Qualified for Automotive Applications
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.3 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

SN74LVC2G125-Q1 应用技术支持与电子电路设计开发资源下载

1. SN74LVC2G125-Q1 数据资料 dataSheet 下载.PDF
2. TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
3. CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
4. Semiconductor Packing Methodology (PDF 3005 KB)
5. 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
6. 标准线性和逻辑产品 5 分钟指南 (786KB)
7. 了解和解释标准逻辑数据表
8. LOGIC Pocket Data Book (PDF 6001 KB)
9. HiRel Unitrode Power Management Brochure (PDF 206 KB)
10. Logic Cross-Reference (PDF 2938 KB)