This Evaluation Module (EVM) facilitates the experimental testing of the Texas Instruments SN65LVDS17 Repeater/Translator silicon device. This device accepts fully differential PECL, CML or LVDS input levels and Translates them to LVDS output levels as defined by TIA/EIA-644-A standard.
The device operates at rates to 4.0Gbps or clock rates to 2.0 GHz at either 3.3 V or 2.5 V supply operation, with typically 110 ns of Intrinsic Phase Jitter.
The device output can be disabled to the high impedance state by applying a logic High level to the EN bar pin.
This device also provides a voltage reference output (Vbb) of typically 1.35 V below Vcc for use in receiving single-ended PECL input signals. The Q-bar output pin provides a single-ended output of 575 mV amplitude
| 器件型号 | 名称 | 产品系列 |
| SN65LVDS17 | 具有使能端的 2.5V/3.3V 振荡器增益级/缓冲器 | LVDS/SN65LVDS17/ECL/CML |
