HMC1032LP6GE Clock Generator with Fractional-N PLL & Integrated VCO SMT, 125 - 350 MHz
The HMC1032LP6GE is a low-noise, wide-band clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 125 and 350 MHz range. The HMC1032LP6GE features low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance. The HMC1032LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-165 dBc/Hz) makes the HMC1032LP6GE an ideal source for a variety of applications –such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SERDES) circuits, FPGAs and processors. The HMC1032LP6GE can also be used as reference clock and LO for 1G/10G Ethernet line cards as well as jitter attenuation and frequency translation. The differential output of the HMC1032LP6GE includes a 2-bit output amplitude control which may be set via the SPI serial programming interface, and an output Mute function. The Delta-Sigma Modulator of the HMC1032LP6GE features Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with close to 0 Hz frequency error.
技术特性
- Frequency Range: 125 - 350 MHz
- 75 fs RMS Jitter Generation (Typical)
- Exceeds G.8251 & GR-253-CORE
Jitter Specifications
- -165 dBc/Hz Phase Noise floor
- Maximum Phase Detector
Rate 100 MHz
- Figure of Merit (FOM)
-227 dBc/Hz
- 24-Bit Step Size, Resolution
3 Hz Typical
- Exact Frequency Mode
- Built-in Digital Self Test
- 40 Lead 6x6mm SMT Package: 36mm²
订购信息 Ordering Information
应用领域 APPLICATION
- 1G/10G Ethernet Line Cards
- OTN & SONET / SDH Applications
- High Frequency Processor Clocks
- Low Jitter SAW Oscillator
Replacement
- Fiber Channel Interface Clocks
- Cellular/4G Infrastructure
- DDS Replacement
- 10G Optical Modules,
Transponders, Line Cards
|
技术指标
| Freq. (MHz) |
Function |
Typical Phase Jitter (fsRMS) |
Phase Noise (dBc/Hz) |
Max. Ref. Freq. (MHz) |
Typical Power Consumption (W) |
Figure of Merit (Fract/Int) (dBc/Hz) |
Package |
| 125 - 350 |
Clock Generator with Fractional-N PLL + VCO |
116 / 75 |
-165 |
350 |
0.86 |
-227 / -230 |
LP6G |
功能框图 Functional Block Diagram
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