HMC612LP4 75 dB LOGARITHMIC
DETECTOR / CONTROLLER, 50 Hz - 3000 MHz
The HMC612LP4(E) Logarithmic Detector/Controller converts RF signals at its input, to a proportional DC voltage at its output. The HMC612LP4(E) employs a successive compression topology which delivers extremely high dynamic range and conversion accuracy over a wide input frequency range. As the input power is increased, successive amplifi ers move into saturation one by one creating an accurate approximation of the logarithm function. The output of a series of square law detectors is summed, converted into voltage domain and buffered to drive the LOGOUT output. For detection mode, the LOGOUT pin is shorted to the VSET input, and will provide a nominal logarithmic slope of 19mV/dB and an intercept of -95 dBm.The HMC612LP4(E) can also be used in the controller mode where an external voltage is applied to the VSET pin, to create an AGC or APC feedback loop.
技术特性
- Cellular/PCS /3G
- WiMAX, WiBro, WLAN, Fixed Wireless & Radar
- Power Monitoring & Control Circuitry
- Receiver Signal Strength Indication (RSS I)
- Automatic Gain & Power Control
订购信息 Ordering Information
应用领域 APPLICATION
- Wide Input Bandwidth: 50 Hz to 3 GHz
- Wide Dynamic Range: Up to 74 dB
- High Accuracy: ±1 dB with 60 dB Range Up to 0.9 GHz
- Supply Voltage: +2.7V to +5.5V
- Excellent Stability over Temperature
- Power-Down Mode
- Compact 4x4mm Leadless SMT Package
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技术指标
| Freq. (GHz) |
Function |
Gain (dB) |
OIP3 (dBm) |
NF (dB) |
P1dB (dBm) |
Bias Supply |
Package |
| DC - 1 |
HBT Gain Block |
22 |
37 |
2.8 |
22 |
+5V @ 88mA |
ST89 |
功能框图 Functional Block Diagram
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