HMC679LC3C 26 GHz, T Flip-Flop with RESET & Programmable Output Voltage
The HMC679LC3C is a T Flip-Flop w/Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-two function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC679LC3C also features an output level control pin, VR, which allows for loss compensation or for signal level optimization. All input signals to the HMC679LC3C are terminated with 50Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50Ω to a non-ground DC voltage. The HMC679LC3C operates from a single -3.3V dc supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.
技术特性
- Supports Clock Frequencies up to 26 GHz
- Differential & Singe-Ended Operation
- Fast Rise & Fall Times: 18 / 17 ps
- Low Power Consumption: 270 mW typ.
- Programmable Differential
Output Voltage Swing: 600 - 1100 mV
- Propagation Delay: 95 ps
- Single Supply: -3.3V
- 16 Lead Ceramic 3x3mm
SMT Package: 9mm²
订购信息 Ordering Information
应用领域 APPLICATION
- Serial Data Transmission
up to 26 Gbps
- High Speed Frequency Divider
(up to 26 GHz)
- Broadband Test & Measurement
- RF ATE Applications
|
技术指标
Data/
Clock Rate (Gbps/GHz) |
Function |
Rise/Fall Time
(ps) |
Diff. Output Swing (Vp-p) |
DC Power Consumption (mW) |
DC Power Supply (Vdc) |
Package |
| 26 / 26 |
T Flip-Flop w/Reset |
18 / 17 |
0.4 - 1.1 |
270 |
-3.3 |
LC3C |
功能框图 Functional Block Diagram
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