The M34D64-W are I²C-compatible electrically erasable programmable memory (EEPROM) devices organized as 8192 x 8 bits.
These devices are compatible with the I²C memory protocol. This is a two-wire serial interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I²C bus inition.
The device behaves as a slave in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and Read/Write bit (RW) (as described in Table 2.: Device select code), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Generic Part Number |
Storage Capacity |
Serial Interface |
Marketing Status |
Automotive Grade |
Supply Voltage(Vcc) |
Supply Voltage(Vcc) |
Clock Frequency(fSCL) |
Package |
spec | min | max | max | |||||
kB | V | V | MHz | |||||
M24C64-F | 64 | I²C | Active | - | 1.7 | 5.5 | 0.4 | TSSOP8; UFDFPN 2x3x0.6 8L 0.5MM PITCH |
M24C64-R | 64 | I²C | Active | - | 1.8 | 5.5 | 0.4 | SO8; TSSOP8 |
M24C64-W | 64 | I²C | Active | Yes | 2.5 | 5.5 | 0.4 | PDIP8; SO8; TSSOP8 |
M34D64-W | 64 | I²C | Active | - | 2.5 | 5.5 | 0.4 | SO8 |
M95640 | 64 | SPI | Active | Yes | 4.5 | 5.5 | 5 | SO8 |
M95640-R | 64 | SPI | Active | - | 1.8 | 5.5 | 2 | SO8; TSSOP8; UFDFPN 2x3x0.6 8L 0.5MM PITCH |
M95640-W | 64 | SPI | Active | Yes | 2.5 | 5.5 | 5 | SO8; TSSOP8 |