SN74ABT18502 具有 18 位通用总线收发器的扫描测试设备
The SN74ABT18502 scan test device with an 18-bit universal bus transceiver is a member of the Texas Instruments SCOPE™ testability IC family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the four-wire test access port (TAP) interface.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. The device can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary test cells
|
SN74ABT18502 |
| Voltage Nodes(V) |
5 |
| Vcc range(V) |
4.5 to 5.5 |
| Input Level |
TTL |
| Logic |
True |
| No. of Outputs |
18 |
| Output Drive(mA) |
-32/64 |
| tpd max(ns) |
6.2 |
| Output Level |
TTL |
| Static Current |
13 |
| Rating |
Catalog |
| Technology Family |
ABT |
SN74ABT18502 特性
- Member of the Texas Instruments Widebus™ Family
- UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
- Compatible With IEEE Std 1149.1-1990 (JTAG) Test Access Port (TAP) and Boundary-Scan Architecture
- Includes D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
- Two Boundary-Scan Cells (BSCs) Per I/O for Greater Flexibility
- SCOPE™ Instruction Set
- IEEE Std 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ
- Parallel Signature Analysis (PSA) at Inputs With Masking Option
- Pseudorandom Pattern Generation (PRPG) From Outputs
- Sample Inputs/Toggle Outputs (TOPSIP)
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
SN74ABT18502 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74ABT18502PM |
ACTIVE |
-40 to 85 |
20.55 | 1ku |
LQFP (PM) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74ABT18502PMG4 |
ACTIVE |
-40 to 85 |
20.55 | 1ku |
LQFP (PM) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74ABT18502PMR |
ACTIVE |
-40 to 85 |
17.85 | 1ku |
LQFP (PM) | 64 |
1000 | LARGE T&R |
|
| SN74ABT18502PMRG4 |
ACTIVE |
-40 to 85 |
17.85 | 1ku |
LQFP (PM) | 64 |
1000 | LARGE T&R |
|
SN74ABT18502 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74ABT18502PM |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABT18502PM |
SN74ABT18502PM |
| SN74ABT18502PMG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABT18502PMG4 |
SN74ABT18502PMG4 |
| SN74ABT18502PMR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABT18502PMR |
SN74ABT18502PMR |
| SN74ABT18502PMRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74ABT18502PMRG4 |
SN74ABT18502PMRG4 |
SN74ABT18502 应用技术支持与电子电路设计开发资源下载
- SN74ABT18502 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
