SN74GTLPH16927 具有源同步时钟输出的 18 位 LVTTL 到 GTLP 总线收发器
The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer. Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous and clock-synchronous applications. Source-synchronous applications require the skew between the clock output and data output to be minimized for optimum maximum-frequency system performance. In order to reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the device.
|
SN74GTLPH16927 |
| Voltage Nodes(V) |
3.3 |
| Bus Drive(ma) |
-24/24 |
| No. of Bits |
18 |
| Static Current |
50 mA |
| Rating |
Catalog |
| Technology Family |
GTLP |
SN74GTLPH16927 特性
- Member of the Texas Instruments Widebus™ Family
- TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
- OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
- Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
- GTLP Buffered SYSCLK Signal (SSCLK) for Source-Synchronous Applications
- LVTTL Interfaces Are 5-V Tolerant
- Medium-Drive GTLP Outputs (50 mA)
- LVTTL Outputs (–24 mA/24 mA)
- GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
- Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
- Bus Hold on A-Port Data Inputs
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74GTLPH16927 芯片订购指南
SN74GTLPH16927 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74GTLPH16927GQLR |
TBD |
CU SNPB |
Level-2-240C-1 YEAR |
SN74GTLPH16927GQLR |
SN74GTLPH16927GQLR |
| SN74GTLPH16927ZQLR |
TBD |
CU SNPB |
Level-2-240C-1 YEAR |
SN74GTLPH16927ZQLR |
SN74GTLPH16927ZQLR |
SN74GTLPH16927 应用技术支持与电子电路设计开发资源下载
- SN74GTLPH16927 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
- Semiconductor Packing Methodology (PDF 3005 KB)
- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
