SN74LVTH18652A 具有 18 位收发器和寄存器的 3.3V ABT 扫描测试设备
The 'LVTH18652A and 'LVTH182652A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments (TI) SCOPE testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers
|
SN74LVTH18652A |
| Voltage Nodes(V) |
3.3, 2.7 |
| Vcc range(V) |
2.7 to 3.6 |
| Input Level |
TTL/CMOS |
| Logic |
True |
| No. of Outputs |
18 |
| Output Drive(mA) |
-32/64 |
| tpd max(ns) |
6 |
| Output Level |
LVTTL |
| Static Current |
16 |
| Rating |
Catalog |
| Technology Family |
LVT |
SN74LVTH18652A 特性
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
- B-Port Outputs of 'LVTH182652A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
- Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- SCOPE Instruction Set
- IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
- Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings
SN74LVTH18652A 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| SN74LVTH18652APM |
ACTIVE |
-40 to 85 |
18.04 | 1ku |
TSSOP (DGG) | 64 |
160 | JEDEC TRAY (10+1) |
|
| SN74LVTH18652APMG4 |
ACTIVE |
-40 to 85 |
18.04 | 1ku |
TSSOP (DGG) | 64 |
160 | JEDEC TRAY (10+1) |
|
SN74LVTH18652A 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| SN74LVTH18652APM |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74LVTH18652APM |
SN74LVTH18652APM |
| SN74LVTH18652APMG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-3-260C-168 HR |
SN74LVTH18652APMG4 |
SN74LVTH18652APMG4 |
SN74LVTH18652A 应用技术支持与电子电路设计开发资源下载
- SN74LVTH18652A 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
