These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA\) input is low. Taking the output-enable (OEAB\ or OEBA\) input low accesses the data on either port.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended
| SN74LVTH2952 | |
| Voltage Nodes(V) | 3.3, 2.7 |
| Technology Family | LVT |
| Rating | Catalog |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LVTH2952DW | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVTH2952DWE4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE | |
| SN74LVTH2952DWG4 | ACTIVE | -40 to 85 | 1.15 | 1ku | SOIC (DW) | 24 | 25 | TUBE |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LVTH2952DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH2952DW | SN74LVTH2952DW |
| SN74LVTH2952DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH2952DWE4 | SN74LVTH2952DWE4 |
| SN74LVTH2952DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LVTH2952DWG4 | SN74LVTH2952DWG4 |
